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Aricent Technologies Walkin – Engineer / Sr. Engineer / Lead / Manager 24th & 25th September 2016



1. Domain: RTL Design
Skills required: VerilogA/HDL/System Verilog,Lint, CDC, Low power, Synthesis & implementation

2. Domain: Design Verification
Skills required: UVM/OVM, System Verilog,
SoC verification, scripting, coverage, GLS

3. Domain: DFT
Skills required: DFT architecture, SCAN, JTAG,MBIST, Scan insertion & Pattern Simulation

4. Domain: Physical Design Engineer
Skills required: Full chip and block level Netlist to GDS – Implementation and Signoff in sub 20nm nodes

5. Domain: Memory Compilers Circuit and Layout Design
Skills required: Experience in SRAM, Register File, ROM and Custom memories. CMOS circuit design, characterization, layout design, physical verification & reliability checks

6. Domain: Analog / RF Circuit and Layout Design
Skills required: Experience in LDO, PLL, ADC, DAC, Mixers, LNA, VCO etc. CMOS circuit design & verification, layout design, physical verification & reliability checks

7. Domain: STA / Synthesis
Skills required: Synthesis , STA, MMMC, Timing Constraints Dev, OCV and SI enabled signoff expertise

Industry: IT-Hardware / Hardware Services
Functional Area: IT Hardware
Experience: 3 – 12 Years
Location: Bangalore

Interested candidates can walkin on 24th & 25th September 2016 from 10 AM with updated resume
Venue
Hotel Park Plaza,
#90/4 Marathahalli, Outer Ring Road,
Bangalore 560037.
Ph: 08067076909
Email resume to: careers@aricent.com

Company Profile
Aricent is a global design and engineering company innovating for the digital era. With more than 12,000 design and engineering talent and over 25 years of experience,help the world’s leading companies solve their most important business and technology innovation challenges – from Customer to Chip.

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2016-12-04T03:58:47+00:00