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Enlivening Technologies Walk-in – SOC (System Level) Verification RTL Design Engineers (08th October 2016)


Job Description: 1. RTL Design Engineers * ASIC Flows LINT CDC DRC rule checking Synthesis using RTL compiler * Micro-architecture and RTL implementation * Block level / full chip integration and design. * 3+ years experience with design, verification and timing tools . * Hands-on with Lint, CDC, LEC preferably Low Power check tools * […]

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