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First Pass Semiconductors Walkin – Design Verification / Physical Design / Analog Layout Engineers 10th Sept 2016



Walkin Interview 10th September 2016 for the following positions

1. Design Verification Engineers
• Candidate should be BE/B.Tech / ME / M.Tech 2 years to 15 years
• Develop verification testbench components for chip/module level using System Verilog, C/C++.
• Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
• Define and execute detailed verification plan from spec working with architects, designers, system engineers.
• Write tests, Debug tests, automate regression scripts and regression environment.
• Good written and oral communication skills.
• Ability to interface with different teams and prioritize work based on project needs.

2. Analog Layout Engineers
• Candidate should be BE / B.Tech / ME / M.Tech 3 years to 15 years
• He/She should be able to act as focal point with customers, work and lead a team of 3-4 custom layout engineers on analog layout, physical verification, maintaining PDKs, ealuating them.
• Candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO. He/She should be able to adapt to new technologies/tools/flows pretty quickly.
• Strong basics in process technology, fabrication techniques.
• Good written and oral communication skills.
• Ability to interface with different teams and prioritize work based on project needs.

3. Physical Design Engineers
• Candidate should be BE / B.Tech / ME / M.Tech 3 years to 15 years.
• He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks

• He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
• Provide technical guidance, mentoring to physical design engrs.
Interface with front-end ASIC teams to resolve issues.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills.
• Ability to interface with different teams and prioritize work based on project needs.

Interested candidates can walkin on 10th September 2016 from 10 am with updated resume & photograph
Venue
First Pass Semiconductors
2nd floor, Plot No: 11, Shilpi Valley,
Madhapur, Hyderabad – 500 081,
India.
Telephone: +91 040 40258899
Email id: jobs@firstpass-semi.com

Company Profile
Founded in the December of 2010 by a group of VLSI professionals with an in depth knowledge and experience of more than 20+ years in the field of ASIC design, the First Pass Semiconductors technical team has cumulatively worked on more than 90+ ASIC tape outs.

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2016-12-05T20:37:50+00:00